1. Field of the Invention
The present invention relates to field-effect transistors.
2. Description of Related Art
Field-effect transistors (hereafter referred to “FETs”) with higher power and higher efficiency are demanded for the amplifiers used in the cellular base-stations, with the advance of telecommunication technology.
To date, Si-MOSFET (Metal-Oxide-Semiconductor FET), GaAs-MESFET (Metal-Semiconductor FET), and GaAs-HJFET (Hetero-Junction FET) have been used as the conventional Power FETs. HJFET is also referred to as HEMT (High Electron Mobility Transistor).
In recent years, “GaN-FET”, which uses a wide band gap semiconductor GaN realizing high temperature operation, has been proposed as a high power FET.
GaN substrate for GaN epitaxial growth is difficult to make. Therefore, it is usually grown on the foreign substrates such as sapphire, SiC or Si.
In particular, Si has higher thermal conductivity than sapphire. The large diameter Si substrate is made easier than the SiC substrate, so that it allows the manufacturers to make GaN epitaxial wafers at lower cost. For this reason, in order to encourage the GaN-FETs for consumer devices, it is important to develop a GaN-FET on a Si substrate.
Generally, in order to decrease the substrate parasitic capacitance of a FET for high Radio-frequency (RF) operation, it is desirable to use a semi-insulating substrate. However, Si does not provide a semi-insulating property (1.0×106 Ωcm or more in resistivity) and only Si substrates with a resistivity of 1.0×106 Ωcm or less are available.
In this specification, “resistivity” refers to the value at room temperature (300 K) unless otherwise specified.
Furthermore, in this specification, “high resistivity” is defined as a resistivity whose value is 1.0×102 Ωcm or more and “low resistivity” is defined as a resistivity whose value is 1.0×10−1 Ωcm or less.
In order to decrease the substrate parasitic capacitance, it is desirable to use a high-resistivity Si substrate having a resistivity of 1.0×102 Ωcm or more (from 1.0×102 to 1.0×106 Ωcm).
GaN-FETs which use a high-resistivity Si substrate with the value of 1.0×104 Ωcm are reported in two documents: Piner et al., International Electron Devices Meetings (IEDM) 2006. Proceedings, pp. 1-4, “Device Degradation Phenomena in GaN HFET Technology: Status, Mechanisms, and Opportunities” and Martin et al., Compound Semiconductor Integrated Circuit Symposium (CSICS), 2007. Proceedings pp. 1-4, “High-Power and High-Voltage AlGaN/GaN HEMTs-on-Si”. FIG. 7 is a schematic sectional view of a semiconductor device with a conventional GaN-FET using a high-resistivity Si substrate as discussed in these documents.
As shown in FIG. 7, in a semiconductor device 101, a plurality of FETs 120, each FET having a source electrode 121S, a drain electrode 122D, and a gate electrode 123G, are formed on a GaN epitaxial wafer 110 in which a GaN epitaxial layer 112 has grown on a high-resistivity Si substrate 111 with the value of 1.0×104 Ωcm and an AlGaN layer 113 has grown on it.
In the semiconductor layer including the GaN layer 112 and AlGaN layer 113, a source ohmic contact 125S is formed under each source electrode 121S and a drain ohmic contact 126D is formed under each drain electrode 122D.
In the semiconductor device 101, a high concentration of two-dimensional electron gas (2DEG) is induced by spontaneous and piezoelectric polarization in hetero interface (channel) between the AlGaN layer and GaN one, producing a higher drain current than conventional Si FETs and GaAs ones. So, the GaN-FET can achieve a high power density operation. The source electrode 121S and the back side of the Si substrate 111 are grounded, and a drain voltage in the range of +10 to +50 V is applied to the drain electrode 122D and a gate voltage is applied to the gate electrode 123G to set a required quiescent current.
Since Si has a narrow band gap, the electrons are easily transferred from the valence band to conduction one while the ambient temperature rises, so an intrinsic current flows at a higher temperature. Therefore, as shown in FIG. 8, Si has a temperature dependence of its resistivity, posing a problem that the substrate becomes less resistive at higher temperatures. The larger the resistivity is at room temperature, the more abruptly the resistivity changes. FIG. 8 is a graph which appears in International Series of Monographs on Semiconductors Volume 9 Silicon Semiconductor Data, p. 51 (authored by Helmut F. Wolf and published by Pergamon Press).
For the above reason, as the temperature rises, the parasitic capacitance between the Si substrate and GaN-FET channel increases and as shown in FIG. 9, the drain efficiency tends to decline. FIG. 9 shows measurement data obtained by the present inventors, representing the relation between channel temperature and drain efficiency in the conventional GaN-FET using the high-resistivity Si substrate as shown in FIG. 7.
Generally, it is ideal that the FET operates without a sudden decline in efficiency over the channel temperature of 200° C. Particularly, GaN-FETs are expected to operate at higher temperatures, taking advantage of the characteristics of the wide band gap semiconductor. FIG. 9 also shows an example of temperature dependence of drain efficiency for ideal GaN-FET operation.
The graph of FIG. 8 suggests that the temperature dependence of the resistivity can be suppressed by the use of a low-resistivity Si substrate with a resistivity of 1.0×10−1 Ωcm or less, and the decline of the drain efficiency at high temperatures would be also suppressed. However, a low-resistivity Si substrate would generate a parasitic capacitance even at room temperature, leading to a lower efficiency. For this reason, as far as an existing GaN-on-Si wafer is used, the high temperature operation, which is inherent property in GaN as a wide band gap semiconductor, cannot be sufficiently achieved.
FIG. 10 is a plan view of the FET shown in FIG. 1 of Japanese Unexamined Patent Publication No. Hei 5 (1993)-190574. The source electrode S and drain electrode D are shaped like a lattice and the drain electrode area is decreased.
FIGS. 11 and 12 are plan views of the FETs shown in FIGS. 1 and 4 of Japanese Patent Application Publication No. 2008-518462. In the structure shown in FIG. 11, the width of the drain electrode D is smaller than the width of the source electrode S. In the structure shown in FIG. 12, the drain electrode D is divided into at least two sub-electrodes.
In FIGS. 10 to 12, symbols S, D, and G denote source electrode, drain electrode, and gate electrode respectively.